The AchieVer Posted March 11, 2019 Share Posted March 11, 2019 Open source advances deeper into hardware: The CHIPS Alliance project The Linux Foundation welcomes the CHIPS Alliance Project, with its plans to open-source CPU chip and SoC designs for a new day of hardware innovation. Open-source hardware is older than you might think. Sun released OpenSPARC in 2007, and IBM started OpenPOWER in 2013. OpenSPARC would die after Oracle bought Sun, and OpenPOWER remains largely IBM-driven. With the recent arrival of the RISC-V (pronounced Risk-Five), though, open-source CPU designs have finally caught fire. Now, the Linux Foundation is helping form the CHIPS Alliance project. CHIPS, in turn, will host and curate high-quality, open-source silicon device design code. Backed by Esperanto, Google, SiFive, and Western Digital, the CHIPS Alliance will foster a collaborative environment for creating and deploying new open-source chip designs. These will be used across the entire spectrum of computing. This will include mobile, computing, consumer electronics, and Internet of Things (IoT) chip and System on a Chip (SoC) designs. While these early CHIPS Alliance backers are all committed to the RISC-V architecture, they want to move beyond just RISC-V. They're creating an independent entity for companies and individuals to collaborate and contribute resources to make open-source CPU chip and SOC design more accessible. "Open collaboration has repeatedly proven to help industries accelerate time to market, achieve long-term maintainability, and create de facto standards," said Mike Dolan, the Linux Foundation's vice president of strategic programs, said in a statement. "The same collaboration model applies to the hardware in a system, just as it does to software components. We are eager to host the CHIPS Alliance and invite more organizations to join the initiative to help propel collaborative innovation within the CPU and SoC markets." Each of these early member companies are open-sourcing a wide variety of technologies. These include: Google: A Universal Verification Methodology (UVM) based instruction stream generator environment for RISC-V cores. This environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs. I should also point out that Google has been hiring chip engineers in recent months. SiFive: RocketChip SoC generator; TileLink interconnect fabric; Chisel, a new open-source hardware description language; and the FIRRTL intermediate representation specification and transformation toolkit. The company, founded by RISC-V's inventors, will also contribute and maintain Diplomacy, the SoC parameter negotiation framework. Western Digital: Its high performance, 9-stage, dual issue, 32-bit SweRV core, together with a test bench, and high performance SweRV instruction set simulator. WD will also contribute the specification and early implementations of OmniXtend cache coherence protocol. Looking ahead, in a statement, Dr. Amir Salek, Google Cloud's senior director of Technical Infrastructure, said: "We are entering a new golden age of computer architecture highlighted by accelerators, rapid hardware development and open source architecture and implementations. The CHIPS Alliance will provide the support and framework needed to nurture a vibrant open-source hardware ecosystem for high-quality, well-verified and documented components to accelerate and simplify chip design." Specifically, Yunsup Lee, SiFive's co-founder and CTO, hopes CHIPS will reboot chip design. "Semiconductor design starts have evaporated due to the skyrocketing cost of building a custom SoC. A healthy, vibrant semiconductor industry needs a significant number of design starts, and the CHIPS Alliance will fill this need," Lee said. Dr. Zvonimir Bandic, Western Digital's senior director of next generation platforms architecture ahd co-founder of RISC-V added: "The CHIPS Alliance will provide access to an open-source silicon solution that can democratize key memory and storage interfaces and enable revolutionary new data-centric architectures. It paves the way for a new generation of compute devices and intelligent accelerators that are close to the memory and can transform how data is moved, shared, and consumed across a wide range of applications." Once upon a time, and it wasn't that long ago, innovation rules in chip design. With the fresh air of open source blowing through processors, perhaps we'll see those days returned. With all the inherent security problems revealed in the dominant x86 processor world by the Meltdown and Spectre bugs, it's well past time for new ideas. Source Link to comment Share on other sites More sharing options...
Open-source hardware is older than you might think. Sun released OpenSPARC in 2007, and IBM started OpenPOWER in 2013. OpenSPARC would die after Oracle bought Sun, and OpenPOWER remains largely IBM-driven. With the recent arrival of the RISC-V (pronounced Risk-Five), though, open-source CPU designs have finally caught fire. Now, the Linux Foundation is helping form the CHIPS Alliance project. CHIPS, in turn, will host and curate high-quality, open-source silicon device design code. Backed by Esperanto, Google, SiFive, and Western Digital, the CHIPS Alliance will foster a collaborative environment for creating and deploying new open-source chip designs. These will be used across the entire spectrum of computing. This will include mobile, computing, consumer electronics, and Internet of Things (IoT) chip and System on a Chip (SoC) designs. While these early CHIPS Alliance backers are all committed to the RISC-V architecture, they want to move beyond just RISC-V. They're creating an independent entity for companies and individuals to collaborate and contribute resources to make open-source CPU chip and SOC design more accessible. "Open collaboration has repeatedly proven to help industries accelerate time to market, achieve long-term maintainability, and create de facto standards," said Mike Dolan, the Linux Foundation's vice president of strategic programs, said in a statement. "The same collaboration model applies to the hardware in a system, just as it does to software components. We are eager to host the CHIPS Alliance and invite more organizations to join the initiative to help propel collaborative innovation within the CPU and SoC markets." Each of these early member companies are open-sourcing a wide variety of technologies. These include: Google: A Universal Verification Methodology (UVM) based instruction stream generator environment for RISC-V cores. This environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs. I should also point out that Google has been hiring chip engineers in recent months. SiFive: RocketChip SoC generator; TileLink interconnect fabric; Chisel, a new open-source hardware description language; and the FIRRTL intermediate representation specification and transformation toolkit. The company, founded by RISC-V's inventors, will also contribute and maintain Diplomacy, the SoC parameter negotiation framework. Western Digital: Its high performance, 9-stage, dual issue, 32-bit SweRV core, together with a test bench, and high performance SweRV instruction set simulator. WD will also contribute the specification and early implementations of OmniXtend cache coherence protocol. Looking ahead, in a statement, Dr. Amir Salek, Google Cloud's senior director of Technical Infrastructure, said: "We are entering a new golden age of computer architecture highlighted by accelerators, rapid hardware development and open source architecture and implementations. The CHIPS Alliance will provide the support and framework needed to nurture a vibrant open-source hardware ecosystem for high-quality, well-verified and documented components to accelerate and simplify chip design." Specifically, Yunsup Lee, SiFive's co-founder and CTO, hopes CHIPS will reboot chip design. "Semiconductor design starts have evaporated due to the skyrocketing cost of building a custom SoC. A healthy, vibrant semiconductor industry needs a significant number of design starts, and the CHIPS Alliance will fill this need," Lee said. Dr. Zvonimir Bandic, Western Digital's senior director of next generation platforms architecture ahd co-founder of RISC-V added: "The CHIPS Alliance will provide access to an open-source silicon solution that can democratize key memory and storage interfaces and enable revolutionary new data-centric architectures. It paves the way for a new generation of compute devices and intelligent accelerators that are close to the memory and can transform how data is moved, shared, and consumed across a wide range of applications." Once upon a time, and it wasn't that long ago, innovation rules in chip design. With the fresh air of open source blowing through processors, perhaps we'll see those days returned. With all the inherent security problems revealed in the dominant x86 processor world by the Meltdown and Spectre bugs, it's well past time for new ideas. Source
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