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Western Digital’s RISC-V "SweRV" Core Design Released For Free


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Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core. The SweRV core is one of several RISC-V projects the company as undertaken as part of their effort to spearhead the ISA, its ecosystem, and foster their own transition away from licensed, royalty-charging CPU cores. In accordance with the more open design goals of RISC-V, the publication of the high-level representation of SweTV means that third parties can use it in their own chip designs, which will popularize not only the particular core design, but also the RISC-V architecture in general.

The RTL design abstraction of Western Digital’s RISC-V SweRV core is now available at GitHub. The design is licensed under the Apache 2.0 license, which is a very permissive (and non-copyleft) license that allows the core to be used free of charge, with or without modifications, and without requiring any modifications to be released in-kind. In fact the requirements of the license are quite slim; besides requiring appropriate attribution, the only other notable restriction is that third party developers cannot use Western Digital’s brands to mark their work.

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Western Digital’s RISC-V SweRV core is a 32-bit in-order core featuring a 2-way superscalar design and a nine-stage pipeline. When implemented using a 28 nm process technology, the core runs at up to 1.8 GHz. Based on Western Digital’s simulations, the SweRV core delivers 4.9 CoreMark/MHz, which is a bit higher when compared to ARM’s Cortex-A15. The developer of the core plans to use its RISC-V cores for its own embedded designs, such as flash controllers and SSDs, but it is unclear when these chips are set to be available.

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Being one of the major supporters of RISC-V, Western Digital believes that by letting third-parties to use the core it will help to drive adoption of the RISC-V architecture by hardware and software designers. The latter will ensure that Western Digital’s own future designs will get a better support by software developers.

 

 

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