Carbon Nanotube based NRAM now ready for production after 15 years

[Batu69]

The company Nantero has made its Carbon NanoTubes (CNT) memory cells ready for production to use in a system on a chip (SoC) after more than 15 years of the development. Development started in 2001 with the goal to develop non-volatile NRAM memory using carbon nanotubes.

 

 

Today the United States based company announced its first licensee of the technology, Fujitsu Semiconductor. The companies will also work together towards releasing a product based on 55-nm process technology.

 

Nantero’s NRAM has many benefits, it should be able to write data  several 1000 times faster than embedded flash memory and it should also have many thousands of times more rewrite cycles. The memory is as fast as and denser than DRAM, nonvolatile like flash memory, has essentially zero power consumption in standby mode and consumes 160x less write energy per bit than flash.

 

The NRAM works by using carbon nanotubes of which one carbon nanotube is just 1/50,000th the diameter of a human hair. The tiny cylinders are 50 times stronger than steel, half the density of aluminum, and have better thermal and electrical conductivity properties than any other material scientists are aware of today.

 

NRAM is based on forming a film of CNTs that are deposited onto a standard silicon substrate that contains an underlying cell select device and array lines (typically transistors or diodes) that interface with the NRAM switch.  The CNTs in the film are crossed and can be touching or separated.

 

When separated (off), the CNT material resistive state is high and signals a “zero.” A lower resistive state occurs when they touch and that signals a “one.” SET (off to on or 0 to 1) is an electrostatic operation, while RESET (On to off, 1 to 0) is a phonon-driven operation with phonon heating of CNT contacts.

 

NRAM cells can be placed in two or more resistive states, depending upon the resistive state of the CNT fabric. If all the CNTs are switched from touching to separated or vice versa, then that is a 1-bit cell, like SLC flash. But the material can be programmed to move a subset of the 100s of CNTs in a cell from touching to separated or vice versa. If the subset is half the cell’s CNTs then we have a 2-bit cell and four resistive states. Theoretically a design with three subsets gives us a 3-bit cell.

 

The first NRAM chips will be 256 Mbit (32) and Fujitsu Semiconductor plans to develop them as an NRAM-embedded custom LSI product by the end of 2018, with the goal of expanding the product lineup into stand-alone NRAM product after that. In a later stage Fujitsu hopes to move to a 40 nm lithography process and Nantero has stated that one of its partners is already working on 28nm  lithography.

 

Article source

[pc71520]

Better late than...never...